1. Field of the Invention
The present invention relates to electrical circuits, and, in particular, to edge-triggered flip-flops, such as master-slave flip-flops, and level-sense flip-flops, often called latches.
2. Description of the Related Art
A master-slave flip-flop is an electrical device that temporarily stores data, where the data is transferred into and within the device on the edges of clocking signals. The master stage of such a flip-flop stores data received at an input port D during one phase of a two-phase clock. On the opposite phase of the two-phase clock, the slave stage stores the data received from the master stage and presents that stored data at an output port Q of the master-slave flip-flop.
FIG. 1 shows a schematic drawing of a prior-art implementation of a static master-slave flip-flop 100 that relies on switched feedback techniques to retain data. Flip-flop 100 comprises four switches S1-S4 and four drivers D1-D4 (implemented using inverters INV1-INV4, respectively) arranged and operated to move data through flip-flop 100 in a particular manner. Flip-flop 100 has a master stage, consisting of switches S1 and S2 and inverters INV1 and INV2, and a slave stage, consisting of switches S3 and S4 and inverters INV3 and INV4.
The master and slave sections of flip-flop 100 each provide memory. This is achieved by feeding back a signal from the output of each stage to its input, thereby holding the output at its present value. If the driver in each stage is inverting, then the feedback path in each stage must also be inverting to provide this memory property.
Switches S1-S4 are controlled by the levels of a two-phase clock, such that switches S1 and S4 are opened when switches S2 and S3 are closed, and vice versa. When switches S1 and S4 are closed and switches S2 and S3 are open, the master stage receives a data signal from input node D. When switches S1 and S4 are open and switches S2 and S3 are closed, data stored in the master stage is passed to the slave stage and output Q. When switches S1 and S4 are closed again and switches S2 and S3 are opened again, the data received by the slave stage from the master stage is stored in the slave stage and held at output Q, while the master stage receives a new data signal at input D. In this way, master-slave flip-flop 100 temporarily stores data received from an input data stream.
As described, with switch S2 closed and switch S1 open, the master stage of flip-flop 100 functions as a memory element. Switches S1 and S2 are typically transmission gates. The classic CMOS transmission gate is constructed of an N channel transistor and a P channel transistor, where the sources of these two devices are tied together and the drains of these devices are also tied together. When the P and N devices are both on, a low resistance path from source to drain is achieved. Alternately, if the P and N devices are turned off, the switch is considered open. Such a transmission gate is a non-inverting structure.
Flip-flops such as flip-flop 100 of FIG. 1 have certain disadvantages. In particular, the most basic design requires four switches and four inverters, which utilize substantial layout area as well as power.
FIG. 2 shows a schematic drawing of a prior-art implementation of a static master-slave flip-flop 200 that relies on weak feedback techniques to retain data. In flip-flop 200, inverters INV2 and INV4 are weak inverters that are designed to have a very small drive. As such, inverter INV2 can be overdriven easily when switch S1 is closed, and inverter INV4 can be overdriven easily when switch S3 is closed, but inverters INV2 and INV4 will provide enough positive feedback during standby (i.e., when switches S1 and S3, respectively, are opened) to retain information in the flip-flop. Because inverters INV2 and INV4 have very small drives, flip-flop 200 can be designed without switches (such as switches S2 and S4 of FIG. 1) in the feedback paths of the master and slave stages, since the input signals received at nodes I1 and I3 from nodes D and 12, respectively, will be sufficiently large to control the state of inverters INV1 and INV3, no matter what signals are received from weak inverters INV2 and INV4, respectively.
Flip-flop 200 has certain advantages over flip-flop 100 of FIG. 1. First of all, flip-flop 200 has two fewer switches than flip-flop 100. Moreover, flip-flop 200 replaces two of the strong inverters of flip-flop 100 with two weak inverters. As such, flip-flop 200 can be implemented with a smaller layout area.
Another desirable goal (in addition to smaller area) in designing flip-flops is to keep both setup time and clock-to-Q propagation time as short as possible. Setup time refers to the time that it takes to charge the master stage of the flip-flop. Analogously, clock-to-Q propagation time refers to the time that it takes to charge the slave stage of the flip-flop. Referring to FIGS. 1 and 2, setup time is the minimum amount of time that the input value D needs to be applied to the master stage before the master transmission gate S1 is opened and still have the master stage retain the correct input value. Clock-to-Q propagation time is the amount of time between the clock edge that closes slave transmission gate S3 and the correct data value reaching output Q.
It is often desirable to implement a flip-flop with preset and/or clear functionality. A preset condition configures the flip-flop to have an output value Q of 1, while a clear condition configures the flip-flop to have an output value Q of 0. FIGS. 3-5 show three different prior-art implementations of static master-slave flip-flops having logic added to support both preset and clear functionality.
FIG. 3A shows a static feedback flip-flop 300 with transmission gate switches in the master and slave feedback loops, similar to flip-flop 100 of FIG. 1. In flip-flop 300, drivers D1 and D4 are both implemented using a gate structure with OR and NAND gate functionality, with preset signal PD and clear signal CDN applied to those drivers to achieve the desired flip-flop preset and clear functionalities. FIGS. 3B and 3C show how the clock signal CKN and the preset signal PD are generated from the input clock signal CK and the input preset signal PDN, respectively.
Referring again to FIG. 3A, the setup time for flip-flop 300 is proportional to the capacitance at node i1. Similarly, the clock-to-Q propagation time for flip-flop 300 is proportional to the capacitance at node i3. In general, the lower the capacitances at nodes i1 and i3, the lower the setup time and clock-to-Q propagation time, respectively. One of the disadvantages of the design of flip-flop 300 is that the implementation of driver D1 as a relatively complex gate structure with applied preset and clear signals greatly increases the effective capacitance at node i1 for a given drive capability of driver D1 (as compared with using an inverter for driver D1), thereby greatly increasing the setup time for flip-flop 300. Moreover, the use of gate structures for drivers D1 and D4 increases the layout size for flip-flop 300, relative to a flip-flop implemented using simple inverters for drivers.
FIG. 4A shows a static weak-keeper feedback flip-flop 400, similar to flip-flop 200 of FIG. 2. As was the case with flip-flop 200, using weak keepers in the feedback paths of flip-flop 400 eliminates the need for feedback switches (e.g., switches S2 and S4 in FIG. 1) and allows all four drivers to be implemented using simple inverters, thereby decreasing the layout of flip-flop 400 relative to flip-flop 300 of FIG. 3. FIG. 4B shows how the clock signals CKX and CKY are generated from the input clock signal CK, the input preset signal PDN, and the input clear signal CDN. Similarly, FIGS. 4C and 4D show how the clear signal CD and the preset signal PD are generated from the input clear signal CDN and the input preset signal PDN, respectively.
In flip-flop 400, the feedback loop in the slave stage is implemented separate from output driver D3 in order to limit feedback contention time and protect the flip-flop state from external changes to Q. Feedback contention refers to the tendency of an ungated feedback loop to resist changes in signal level (even when the feedback driver is a weak keeper as in flip-flop 400) due to the time that it takes for the signal to propagate through the feedback path, thereby increasing the time that it takes to change the signal level at the feedback-loop input node (in this case, node i3).
Unfortunately, the existence of feedback contention in the ungated master feedback loop does adversely affect the setup time of flip-flop 400. Moreover, the presence of preset and clear devices tied directly to nodes i1 and i3 in flip-flop 400 further increases the capacitances at nodes i1 and i3, thereby increasing both setup time and clock-to-Q propagation time. In addition, the application of present and clear signals in the clocking scheme of FIG. 4B further increases clock-to-Q propagation time for flip-flop 400.
FIG. 5A shows static feedback flip-flop 500, which is a hybrid of the flip-flops of FIGS. 3 and 4. FIG. 5B shows how the clock signals CKN and CKA are generated from the input clock signal CK, and FIG. 5C shows how the preset signal PD is generated from the input preset signal PDN. As a hybrid, flip-flop 500 has a master stage, similar to that of flip-flop 300 of FIG. 3, with gated feedback and a complex gate transmission driver with preset and clear inputs, and a slave stage, similar to that of flip-flop 400 of FIG. 4, with preset and clear devices tied directly to node i3 and a feedback loop separate from the output transmission driver. As such, flip-flop 500 has capacitance problems, at node i1, similar to those in the master stage of flip-flop 300 and, at node i3, similar to those in the slave stage of flip-flop 400, which will increase setup time and clock-to-Q propagation time, respectively. Feedback contention in the master stage of flip-flop 500 will also adversely affect setup time.
In the master stage of flip-flop 500, the feedback path has an inverter (e.g., D2 of FIG. 1) combined with a switch (e.g., S2 in FIG. 1) into a gated inverter configuration. In flip-flop 500, the gated inverter structure comprises P channel devices MP1 and MP2 and N channel devices MN1 and MN2, where the MP1 and MN1 devices provide the inverter function, and the MP2 and MN2 devices provide the gating function. When clock signal CKA is 1 and clock signal CKN is 0, the gate is open and node i1 is isolated from the driver output (i.e., node i2).
In the gated inverter structure in the master stage of flip-flop 500, the sources of the devices that perform the gating function are not connected to each other and the drains of those devices are also not connected to each other, as in the typical transmission gate described earlier with reference to flip-flop 100 of FIG. 1. Note that the inverter and gating functions may be reversed such that MP1 and MN1 provide the gating function and MP2 and MN2 provide the inverter function. In this case, either the sources of the devices that form the gating function will be connected to each other or the drains of those devices will be connected to each other, but not both the sources and the drains.